This application incorporates by reference Taiwanese application Serial No. 89126648, filed on Dec. 13, 2000.
1. Field of the Invention
The invention relates in general to a Viterbi detector for partial response maximum likelihood (PRML) signal processing, and more particularly to a Viterbi detector capable of varying sampling rate and using different parameters for PRML signal processing and capable of being implemented with a single piece of hardware.
2. Description of the Related Art
While various approaches to recording information codes in a recording medium are provided for the improvement of information access density, partial response maximum likelihood (PRML) signal processing, is widely used in recording medium systems, such as optical disk systems.
In the process of transmitting signals, when the channel bandwidth is lower than the bandwidth of the signals transmitted in the channel, inter-symbol interference (ISI) occurs in adjacent bits of the signals in the receiving end. When ISI is serious, it may cause jitter. As the recording density of optical disks increases, jitter caused by ISI becomes more serious, increasing the difficulty in phase-locking. For overcoming this phenomenon, the principle of partial response (PR) channel is applied. In PRML signal processing, the channel response is appropriately equalized in a channel response in terms of a PR polynomial. In this way, ISI is constrained and is in an expectable characteristic, resulting in reduction of jitter when ISI occurring. Thus, the performance of phase-locking is improved. In other words, PRML is potentially a technique of improving the recording density of optical disks.
The PRML signal processing includes the following steps. At first, information codes are read from an optical disk. Then the information codes are inputted to a PR equalizer to perform waveform equalization. Next, detection is performed on the output signal of the PR equalizer by using Viterbi algorithm.
Referring to FIG. 1, it illustrates a PRML signal processing apparatus using mark edge (ME) recording method. In FIG. 1, modulated information code E is first inputted into a return-to-zero inversion (NRZI) circuit 102. The modulated information code signal E is then processed by an exclusive-OR gate 104 and a delay element 106 of the NRZI circuit 102, resulting in an output signal F of the NRZI circuit 102. After that, the output signal F of the NRZI circuit 102 is written to a recording medium 108, such as an optical disk. In addition, when the information code signal E has a rising edge, the output signal F of the NRZI circuit 102 has a signal level change, such as a change from zero to one, or from one to zero.
As an example of PRML signal processing, in FIG. 1, PR(1, 2, 1) equalization for the output signal F of the NRZI circuit 102 is performed, and the minimum code reversal distance xcex4 is set to two, wherein xcex4=2 indicates that there are at least two xe2x80x9c0xe2x80x9dbetween adjacent xe2x80x9c1xe2x80x9d in the input signal E of the NRZI circuit 102.
Referring now to FIG. 2, it illustrates the waveforms of the signals in FIG. 1 and corresponding pits on the optical disk, where the signals include the information code signal E, output signal F of the NRZI circuit, reproduction signal G, output signal Jxe2x80x2 of the PR equalizer, and output signal Z of the Viterbi detector. In FIG. 2, the bit sequence in (a) corresponds to an example the information code signal E while the bit sequence in (b) illustrates the corresponding output signal F of the NRZI circuit 102. When the information code signal E has a signal level change of rising edge, the signal Z has a signal level change of itself as well; otherwise, the signal level of the signal Z remains unchanged. The signal in (c) is the LD driving signal produced according to the signal F and is used for controlling a LD (not shown in Figures) to perform write operation on the optical disk. Illustration in (d) is to show the pits on the optical disk which the LD performs the write operation on. The signal of (e) is the reproduction signal G corresponding to the data read from the optical disk by using the optical head. The signal of (f) is the output signal Jxe2x80x2 of the PR equalizer 110 after the PR(1, 2, 1) process. And the signal of (g) is the output signal Z of the Viterbi detector 112 obtained after processing the signal Jxe2x80x2. The PR equalizer 110 and Viterbi detector 112 are called a reproduction signal processing unit 114.
In addition, the output signal of Viterbi detector 112 is in terms of NRZI signal. When the output signal F of the NRZI circuit 102 has a signal level change of either rising edge or falling edge, the corresponding output signal Z of the Viterbi detector 112 is set to one; otherwise, it is set to zero.
In FIG. 2, when the signal F is in a 1 state, the LD driving signal is in the high level and a pit is correspondingly produced on the optical disk.
The reproduction signal processing unit 114 is used for generating the output signal Z of the Viterbi detector 112 by using the reproduction signal G, where the signal Z is theoretically identical to the information code signal E.
The PR equalizer 110 is employed to perform PR(1, 2, 1) equalization. The characteristic of PR(1, 2, 1) equalization is:
Jxe2x80x2(t)=0.25 G(txe2x88x921)+0.5 G(t)+0.25 G(t+1), 
Where Jxe2x80x2(t) denotes the value of output signal Jxe2x80x2 of the PR equalizer at time t, G(txe2x88x921), G(t), and G(t+1) denote the values of reproduction signal G at times txe2x88x921, t, and t+1 respectively.
As shown in FIG. 2 (f), the signal Jxe2x80x2 at each point of time is close to one of four levels {0, 0.25, 0.75, 1} (indicated by four parallel lines). Then, the signal Jxe2x80x2 is inputted to the Viterbi detector 112. Finally, the Viterbi detector 112 produces the output signal Z, which is identical to the information code signal E.
Viterbi detector 112 further stores signal level transition patterns of the output signal Jxe2x80x2 of the PR equalizer 110 corresponding to each point of time in the form of a trellis. In addition, the Viterbi detector 112 only outputs binary signal 0 or 1 at each point of time. Moreover, when the PR equalizer""s output signal Jxe2x80x2 has noise, the Viterbi detector 112 selects the nearest signal level transition pattern and stores the selected transition patterns in Viterbi detector 112.
Referring to FIG. 3, it illustrates a structure of the conventional PR equalizer in FIG. 1. The PR equalizer 110 includes a plurality of delay units (for example, delay units 302, 304, and 306), a plurality of multipliers (for example, multipliers 308, 310, 312, and 314), and an adder 316. The delay units are connected in series and delay respective input signals for one time unit. In this way, the signal G is delayed by the delay units, resulting in signals iN, iNxe2x88x921, iNxe2x88x922, . . . , i1 associated with different delay periods. The signals iN, iNxe2x88x921, iNxe2x88x922, . . . , i1 are then multiplied by coefficients C1, C2, C3, . . . , CN respectively, and the products are inputted to the adder 316. The sum of iN C1, iNxe2x88x921C2, iNxe2x88x922C3, . . . , i1CN is the output of the adder 316, regarding as the output signal Jxe2x80x2 of the PR equalizer 110, where the values of C1, C2, C3, . . . , CN are associated with the parameters of the PR equalization.
Referring to FIG. 4, it illustrates the Viterbi detector 112 in FIG. 1 in block diagram form. The Viterbi detector 112 includes a branch metric calculation circuit 402, an add-compare-and-select (ACS) circuit 404 and a path memory unit 406. The branch metric calculation circuit 402 is for receiving the output signal Jxe2x80x2 of the PR equalizer 110 and calculating the values B0001, B0002, B0011, B0111, B1001, B1101, B1111, and B1112, called the branch metrics. The ACS circuit 404 is for outputting a path memory control signals H000 and H111 based on the branch metrics above. The path memory unit 406 is controlled by the path memory control signals H000 and H111, outputting the output signal Z of the Viterbi detector 112.
FIG. 5 is a block diagram of the branch metric calculation circuit 402 in FIG. 4. The branch metric calculation circuit 402 includes four subtractors 502, four multiplier 504, and four registers 506. In FIG. 4, the subtractors 502 respectively calculate Jxe2x80x2xe2x88x920, Jxe2x80x2xe2x88x920.25, Jxe2x80x2xe2x88x920.75, and Jxe2x80x2xe2x88x921. Next, the outputs of the subtractors are respectively processed by the multipliers 504 for obtaining the respective squares. Then, the four squares of the difference of the PR equalizer output signal Jxe2x80x2 and four equalization-aimed values {0, 0.25, 0.75, 1} are stored in the delay units 506 respectively. The branch metric calculation circuit 402 outputs the branch metrics B0001, B0002, B0011, B0111, B1001, B1101, B1111, and B1112 respectively. For each point of time, the branch metrics are as follows:
B0001=B0002=(0xe2x88x92Jxe2x80x2)2,
B0011=B1001=(0.25xe2x88x92Jxe2x80x2)2,
B0111=B1101=(0.75xe2x88x92Jxe2x80x2)2, and
B1111=B1112=(1.0xe2x88x92Jxe2x80x2)2.
Referring now to FIG. 4, the branch metrics are inputted into the ACS circuit 404. The branch metrics represent the degree and nearness of the PR equalizer output signal Jxe2x80x2 obtained from the PR(1, 2, 1) equalization of the reproduction signal, and the ideal PR(1, 2, 1) equalization signal.
Referring to FIG. 6, it illustrates the ACS circuit 404 in FIG. 4 in a block diagram. The ACS circuit 404 uses six path metrics, P000, P001, P011, P100, P110, and P111, and the initial values of them are set to zero. The ACS circuit 404 derives the path metric at time t from the branch metric at time txe2x88x921 and performs comparison of P000(t)+B0001(t) and P100(t)+B1002(t) as well as P011(t)+B1111(t) and P111(t)+B1112(t). From this, the ACS circuit 404 determines and outputs the path control signals H000(t) and H111(t).
When P000(t+1)+B0001(t)=min{P000(t)+B0001(t), P100(t)+B0002(t)}, H000(t) is equal to zero. When P100(t+1)+B0002(t)=min{P000(t)+B0001(t), P100(t) +B0002(t)}, H000(t) is equal to one.
When P011(t+1)+B1111(t)=min{P011(t)+B1111(t), P111(t)+B1112(t)}, H111(t) is equal to zero. When P111(t+1)+B1112(t)=min{P011(t)+B1111(t), P111(t) +B1112(t)}, H111(t) is equal to one.
Further, the ACS circuit 404 updates the values of the path metrics P000(t+1), P001(t+1), P011(t+1), P100(t+1), P110(t+1), and P111(t+1) according to the following expressions:
P000(t+1)=min{P000(t)+B0001(t), P100(t)+B0002(t)},
P001(t+1)=P000(t)+B0011(t),
P011(t+1)=P001(t)+B0111(t),
P100(t+1)=P110(t)+B1001(t),
P110(t+1)=P111(t)+B1101(t), and
P111(t+1)=min{P011(t)+B1111(t), P111(t)+B1112(t)}.
In FIG. 6, adder 602 is used to sum its two inputs, the comparator 604 and the selector 606 are used for performing the operation of min{x, y}, that is, selecting the smaller one from the parameters x and y. The register 608 is to hold the path metric values.
Referring to FIG. 7, it illustrates path memory unit 406 in FIG. 4. The path memory unit 406 includes n detection sequence switches 7021, to 702n, and 6(nxe2x88x921) delay units 704, where n is an integer greater than one. Two adjacent detection sequence switches are coupled by using six of the delay units 704 in parallel. In addition, the path control signals H000 and H111 are inputted to the detection sequence switches 7021 to 702n respectively. At every time t, the path memory unit 406 outputs a binary signal.
Referring to FIGS. 8A-8D, they illustrate the connection and switching relation between inputs and outputs of the detection sequence switches 7021 to 702n, wherein X, and Yi respectively represent an input and output of one of the detection sequence switches 7021 to 702n and i is an integer. If an input and an output are connected, it is represented by a line connecting two circles indicating the input and output. The dotted line indicates that the two circles (an input and an output) at the ends of the dotted line are not connected. To be specific, FIGS. 8A-8D indicate the connection of the inputs and outputs of the detection sequence switches 7021 to 702n for the path memory signals (H000, H111)=(0, 0), (0, 1), (1, 0), and (1, 1) respectively.
For example, the operation of the detection sequence switches 7021 to 702n in FIG. 7 for (H000, H111)=(0, 0) is described as follows. The delay units 704 receive the output values of one of the detection sequence switches, delay them for one time unit T, and then outputs delayed values of the detection sequence switch to the next detection sequence switch. Each of the detection sequence switches 7021 to 702n includes six input terminals X1 to X6, and six output terminals Y1 to Y6. The path memory unit 406 uses the output signal at the output terminal Y1 of the detection sequence switch 702n as the output signal of the path memory unit 406, that is, the output signal Z of the Viterbi detector for {0, 1}.
Referring to FIG. 9, it illustrates a trellis diagram of signal level transition rule. In FIG. 9, after PR(1, 2, 1) equalization, the output signal Jxe2x80x2 of the PR equalizer 110 has a minimum code reversal distance equal to two, and the associated transition rule is shown in FIG. 2. In addition, the connection of the detection sequence switches 7021 to 702n in FIG. 7 is according to the trellis diagram. In FIG. 9, when the output of the Viterbi detector 112 is an NRZI signal, the output bits and reference levels are indicated after branch (000, 000) 902, branch (100, 000) 904, branch (000, 001) 906, branch (001, 011) 908, branch (110, 100) 910, branch (111, 110) 912, branch (011, 111) 914, and branch (111, 111) 916 respectively. When the output of the Viterbi detector 112 is an NRZ signal, the output bits and reference levels are indicated in the right side of FIG. 9 and associated with the branches 902 to 916 respectively.
In FIG. 9, each circle represents a state in the trellis diagram and the branches connect states at time t with states at time txe2x88x921. The connection of the branches determines the connection of the detection sequence switches 7021 to 702n. The signal Jxe2x80x2 outputted by the PR equalizer 110 has six states: S000, S001, S011, S100, S110, and S111. In FIG. 9, the reference levels define the four equalization-aimed values {0, 0.25, 0.75, 1} in FIG. 5 while the output bits define the values of V1, V2, V3, V4, V5, and V6 in FIG. 7.
In FIG. 9, branch (x, y) indicates a transition from a state Sx at time txe2x88x921 to a state Sy at time t. In addition, branch (000, 000) 902, branch (100, 000) 904, branch (000, 001) 906, branch (001, 011) 908, branch (110, 100) 910, branch (111, 110) 912, branch (011, 111) 914, and branch (111, 111) 916 are associated with the branch metrics B0001, B0001,B0002, B001, B011, B100, B110, B1111, and B1112respectively. In another aspect, a branch metric indicates the cost of a transition from a state at time txe2x88x921 to a state at time t. In this way, the Viterbi detector 112 is to calculate the cost of each path through the branch metrics as so to obtain a path control signal (H000, H111) with the minimum cost. According to the path control signal (H000, H111), the Viterbi detector 112 selects one of the connections of the inputs and outputs of the detection sequence switches 7021 to 702n as illustrated in FIGS. 8A-8D as so to obtain the output signal Z of the Viterbi detector 112.
The structure of the conventional PRML signal processing apparatus described above is to improve the data correctness when data are read from the recording medium, such as an optical disk. However, it is difficult to implement a high speed optical disk system with the conventional structure. For example in a sixteen times digital video disk (DVD) system, the time interval between adjacent data units to be read is only 2.4 ns and thus it is too difficult for the conventional PRML signal processing apparatus to fulfil this requirement.
Besides, when PR equalization is to be performed with another parameters, such as performing PR(1, 1), PR(1, 2, 1), PR(1, 1, 1, 1), or PR(1, 2, 0, 2, 1), the hardware structure of the Viterbi detector 112 have to be modified to fulfil this requirement. In this way, the conventional structure brings inconvenience in application and design of system with the requirement.
It is therefore an object of the invention to provide a Viterbi detector for partial response maximum likelihood (PRML) signal processing apparatus. The Viterbi detector according to the invention can be used for different PRML signal processing apparatuses such as high speed optical disk systems. In addition, the Viterbi detector can perform PR equalization with different parameters. In this way, the Viterbi detector has advantages of saving hardware space and conveniently changing PR equalizations with different parameters.
The invention achieves the above-identified objects by providing a Viterbi detector for use in a PRML signal processing apparatus, wherein the PRML signal processing apparatus includes a partial response (PR) equalizer outputting a PR equalizer output signal serially. The PR equalizer operates at a first frequency and the Viterbi detector operates at a second frequency. The Viterbi detector is used for receiving the PR equalizer output signal and is capable of performing Viterbi detection according to PR equalizations with a plurality of sets of parameters in the PR equalizer. The Viterbi detector includes an input buffer, a branch metric calculation unit, an add-compare-select (ACS) circuit, a path memory unit, and a clock buffer. The input buffer is for receiving the PR equalizer output signal, and selectively outputting the PR equalizer output signal serially or in parallel, according to the first frequency and the second frequency. The branch metric calculation unit is employed to receive the PR equalizer output signal outputted by the input buffer and receive a reference level value stored in a reference level register so as to obtain a plurality of branch metrics. The ACS circuit is then to receive the branch metrics, calculate a plurality of path metrics, and obtain a plurality of path control signals. The path memory unit, includes a detection sequence switch, is used for receiving the path control signals, using an output bit value stored in a storage unit as an input to the detection sequence switch, and outputting a Viterbi detector output signal. The clock buffer is to generate a clock signal at the second frequency and output the clock signal at the second frequency to the branch metric calculation unit, the ACS circuit, and the path memory unit.
The detector sequence switch is operative according to a union trellis diagram relation, wherein the union trellis diagram relation is obtained by combining trellis diagram relations associated with the PR equalizations with the sets of parameters in the PR equalizer and setting the PR equalizer and the Viterbi detector operating at the first frequency and the second frequency respectively. The union trellis diagram relation indicates a plurality of sets of output bits and a plurality of sets of reference levels which are associated with the PR equalizations with the sets of parameters respectively. The output bits are stored in the storage unit while the reference levels are stored in the reference level register. According to the first, second frequencies, and the PR equalization with the set of parameters, the storage unit and the reference level register output the output bit value and the reference level value respectively.